Fujitsu FR family 32-bit microcontroller instruction manue Uživatelský manuál

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Strany 1 - INSTRUCTION MANUAL

FUJITSU SEMICONDUCTORCONTROLLER MANUALFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUALCM71-00101-5E

Strany 2

vi CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ... 535.1 Pipeline Operation ...

Strany 3

76CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.5 ADDN (Add Word Data of Source Register to Destination Register)Adds the word data in "Rj" an

Strany 4

77CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.6 ADDN (Add Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit immedi

Strany 5 - ■ Trademark

78CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.7 ADDN2 (Add Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit immed

Strany 6 - ■ Organization of this manual

79CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.8 SUB (Subtract Word Data in Source Register from Destination Register)Subtracts the word data in "

Strany 7

80CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)Subtracts the word

Strany 8

81CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.10 SUBN (Subtract Word Data in Source Register from Destination Register)Subtracts the word data in &quo

Strany 9 - CONTENTS

82CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.11 CMP (Compare Word Data in Source Register and Destination Register)Subtracts the word data in "R

Strany 10

83CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.12 CMP (Compare Immediate Data of Source Register and Destination Register)Subtracts the result of the h

Strany 11

84CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.13 CMP2 (Compare Immediate Data and Destination Register)Subtracts the result of the higher 28 bits of 4

Strany 12

85CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.14 AND (And Word Data of Source Register to Destination Register)Takes the logical AND of the word data

Strany 13

vii7.35 MULU (Multiply Unsigned Word Data) ... 1227.36 MULH

Strany 14

86CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.15 AND (And Word Data of Source Register to Data in Memory)Takes the logical AND of the word data at mem

Strany 15 - Main changes in this edition

87CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: AND R2, @R3R2 123456781234567C 1111 0000123 4 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

Strany 16

88CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.16 ANDH (And Half-word Data of Source Register to Data in Memory)Takes the logical AND of the half-word

Strany 17

89CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ANDH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 1234

Strany 18

90CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.17 ANDB (And Byte Data of Source Register to Data in Memory)Takes the logical AND of the byte data at me

Strany 19

91CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ANDB R2, @R3R2 1234567812345679 0000 00101234 5678NZVCCCRR2R3R3CCR0000 11NZVC0000 1234 5

Strany 20

92CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.18 OR (Or Word Data of Source Register to Destination Register)Takes the logical OR of the word data in

Strany 21

93CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.19 OR (Or Word Data of Source Register to Data in Memory)Takes the logical OR of the word data at memory

Strany 22

94CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: OR R2, @R3R2 123456781234567C 1111 00001234 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

Strany 23

95CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.20 ORH (Or Half-word Data of Source Register to Data in Memory)Takes the logical OR of the half-word dat

Strany 24

viii 7.82 MOV (Move Word Data in Source Register to Destination Register) ... 1787.83 MOV (Move Word Data

Strany 25 - FR FAMILY OVERVIEW

96CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ORH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 1234

Strany 26

97CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.21 ORB (Or Byte Data of Source Register to Data in Memory)Takes the logical OR of the byte data at memor

Strany 27 - CHAPTER 1 FR FAMILY OVERVIEW

98CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ORB R2, @R3R2 1234567812345679 0000 00111234 5678NZVCCCRR2R3R3CCR0000 10NZVC0000 1234 56

Strany 28

99CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)Takes the logical exclusive OR

Strany 29 - MEMORY ARCHITECTURE

100CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)Takes the logical exclusive OR of t

Strany 30 - 2.1 FR Family Memory Space

101CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EOR R2, @R3R2 123456781234567C 1111 00001234 5678NZVCCCRR2R3R3CCR0000 1010 1010NZVC0000

Strany 31 - 2.1.1 Direct Address Area

102CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)Takes the logical exclusive O

Strany 32 - 2.1.2 Vector Table Area

103CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EORH R2, @R3R2 123456781234567A 0000 11001234 5678NZVCCCRR2R3R3CCR0000 1010NZVC0000 123

Strany 33

104CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)Takes the logical exclusive OR of

Strany 34 - 2.2 Bit Order and Byte Order

105CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: EORB R2, @R3R2 1234567812345679 0000 00111234 5678NZVCCCRR2R3R3CCR0000 10NZVC0000 1234

Strany 35 - 2.3 Word Alignment

ix7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ... 2407.124 ADDSP (Add Stack

Strany 36

106CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical AND of the

Strany 37 - REGISTER DESCRIPTIONS

107CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BANDL #0, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 11NZVC00001234 5678Memory12345678123

Strany 38

108CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical AND of the

Strany 39 - 3.2 General-purpose Registers

109CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BANDH #0, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 11NZVC00001234 5678Memory12345678123

Strany 40 - ● R15 (Stack Pointer: SP)

110CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical OR of the 4-b

Strany 41 - 3.3 Dedicated Registers

111CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BORL #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 56781234567812345679

Strany 42 - 3.3.1 Program Counter (PC)

112CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical OR of the 4-

Strany 43 - 3.3.2 Program Status (PS)

113CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BORH #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 56781234567812345679

Strany 44

114CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)Takes the logical exclusive O

Strany 45 - Initial value: --00XXXXB

115CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BEORL #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 5678Memory12345678123

Strany 47

116CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)Takes the logical exclusive

Strany 48 - Bit no

117CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: BEORH #1, @R312345678123456791234 5678NZVCCCRR3R3CCR0000 00NZVC00001234 5678Memory12345678123

Strany 49 - 3.3.4 Return Pointer (RP)

118CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory)Takes the logical AND of the 4-bit immediate data an

Strany 50 - ■ Return Pointer Functions

119CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory)Takes the logical AND of the 4-bit immediate data a

Strany 51

120CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.34 MUL (Multiply Word Data)Multiplies the word data in "Rj" by the word data in "Ri"

Strany 52

121CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MUL R2, R3MDH MDL NZVCCCR CCR0000NZVC0010R2 R3 0000 00028000 0001MDH MDL R2 R3 0000

Strany 53

122CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.35 MULU (Multiply Unsigned Word Data)Multiplies the word data in "Rj" by the word data in &qu

Strany 54

123CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULU R2, R3MDH MDL NZVCCCR CCR0000NZVC0010R2 R3 0000 00028000 0001MDH MDL R2 R3 0000

Strany 55 - PROCESSING

124CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.36 MULH (Multiply Half-word Data)Multiplies the half-word data in the lower 16 bits of "Rj" b

Strany 56

125CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULH R2, R3MDH MDL NZVCCCR CCR0000NZVC1000R2 R3 FEDCBA980123 4567MDH MDL R2 R3 FEDCB

Strany 57 - 4.1 Reset Processing

xiMain changes in this editionPage Changes (For details, refer to main body.)-Be sure to refer to the "Check Sheet" for the latest cautions

Strany 58

126CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.37 MULUH (Multiply Unsigned Half-word Data)Multiplies the half-word data in the lower 16 bits of "

Strany 59 - ■ Vector Table Configuration

127CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MULUH R2, R3MDH MDL NZVCCCR CCR0000NZVC0000R2 R3 FEDCBA980123 4567MDH MDL R2 R3 FEDC

Strany 60 - ■ Recovery from EIT handler

128CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.38 DIV0S (Initial Setting Up for Signed Division)This command is used for signed division in which the

Strany 61 - 4.3 Interrupts

129CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV0S R2Example: Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), signed calculationM

Strany 62 - 4.3.1 User Interrupts

130CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.39 DIV0U (Initial Setting Up for Unsigned Division)This command is used for unsigned division in which

Strany 63 - ■ How to Use User Interrupts

131CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV0U R2Example: Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), unsigned calculation

Strany 64

132CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.40 DIV1 (Main Process of Division)This instruction is used in unsigned division. It should be used in c

Strany 65

133CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV1 R2MDH MDL D1 D0 TSCR SCRD1 D0 T000000R200FF FFFFMDH MDL R20000 00010100 00000000 000000

Strany 66 - 4.4 Exception Processing

134CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.41 DIV2 (Correction when Remainder is 0)This instruction is used in signed division. It should be used

Strany 67

135CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DIV2 R2MDH MDL D1 D0 TSCR SCRD1 D0 T000000R200FF FFFFMDH MDL R20000 000F0000 00000000 000F00

Strany 68 - 4.5 Traps

xii 38"4.3.1 User Interrupts" is changed.( "External" → "User" ), ( "external" → "user" )"

Strany 69

136CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.42 DIV3 (Correction when Remainder is 0)This instruction is used in signed division. It should be used

Strany 70

137CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.43 DIV4S (Correction Answer for Signed Division)This instruction is used in signed division. It should

Strany 71 - 4.5.3 Step Trace Traps

138CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.44 LSL (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&quo

Strany 72

139CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.45 LSL (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&quo

Strany 73 - 4.5.5 Coprocessor Error Trap

140CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.46 LSL2 (Logical Shift to the Left Direction)Makes a logical left shift of the word data in "Ri&qu

Strany 74

141CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.47 LSR (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&q

Strany 75 - 4.6 Priority Levels

142CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.48 LSR (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&q

Strany 76

143CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.49 LSR2 (Logical Shift to the Right Direction)Makes a logical right shift of the word data in "Ri&

Strany 77 - FAMILY CPU

144CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.50 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &qu

Strany 78 - 5.1 Pipeline Operation

145CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.51 ASR (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &qu

Strany 79 - Generated Deleted

xiii87"7.15 AND (And Word Data of Source Register to Data in Memory)" is changed.( "Instruction bit pattern : 1000 0100 0010 0011"

Strany 80 - 5.3 Register Hazards

146CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.52 ASR2 (Arithmetic Shift to the Right Direction)Makes an arithmetic right shift of the word data in &q

Strany 81 - ■ Interlocking

147CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)Loads 1 word of immediate data to "R

Strany 82

148CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)Extends the 20-bit immediate data with 12

Strany 83

149CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)Extends the 8-bit immediate data with 24 ze

Strany 84

150CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.56 LD (Load Word Data in Memory to Register)Loads the word data at memory address "Rj" to &qu

Strany 85

151CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.57 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R13 + Rj)"

Strany 86

152CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.58 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R14 + o8 × 4)&

Strany 87 - INSTRUCTION OVERVIEW

153CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.59 LD (Load Word Data in Memory to Register)Loads the word data at memory address "(R15 + u4 × 4)&

Strany 88 - 6.1 Instruction Formats

154CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.60 LD (Load Word Data in Memory to Register)Loads the word data at memory address "R15" to &q

Strany 89

155CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.61 LD (Load Word Data in Memory to Register)Loads the word data at memory address "R15" to de

Strany 90

xiv 136"7.42 DIV3 (Correction when Remainder is 0)" is changed.( "Instruction bit pattern : 1001 1111 0110 0000" is added. )137&q

Strany 91 - INSTRUCTIONS

156CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LD @ R15 +, MDH12345670123456741234 5674R15MDH 8765 43211234567012345674 8765 4321R151

Strany 92

157CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.62 LD (Load Word Data in Memory to Program Status Register)Loads the word data at memory address "

Strany 93

158CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LD @ R15 +, PS12345670123456741234 5674FFFF F8D5PSR15 FFF8 F8C01234567012345674 FFF8 F

Strany 94

159CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.63 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

Strany 95

160CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.64 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

Strany 96

161CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.65 LDUH (Load Half-word Data in Memory to Register)Extends with zeros the half-word data at memory addr

Strany 97 - 10100100 i4 Ri

162CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.66 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

Strany 98 - 10100101 i4 Ri

163CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.67 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

Strany 99

164CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.68 LDUB (Load Byte Data in Memory to Register)Extends with zeros the byte data at memory address "

Strany 100 - Register)

165CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.69 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

Strany 101 - 10100000 i4 Ri

xv163"7.67 LDUB (Load Byte Data in Memory to Register)" is changed.( "Instruction bit pattern : 0000 0010 0010 0011" is added. )16

Strany 102 - 10100001 i4 Ri

166CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.70 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

Strany 103 - Destination Register)

167CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.71 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

Strany 104 - 10101101 Rj Ri

168CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.72 ST (Store Word Data in Register to Memory)Loads the word data in "Ri" to memory address &q

Strany 105

169CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.73 ST (Store Word Data in Register to Memory)Subtracts 4 from the value of "R15", stores the

Strany 106

170CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.74 ST (Store Word Data in Register to Memory)Subtracts 4 from the value of "R15", stores the

Strany 107

171CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.75 ST (Store Word Data in Program Status Register to Memory)Subtracts 4 from the value of "R15&quo

Strany 108 - 10101001 i4 Ri

172CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.76 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

Strany 109

173CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.77 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

Strany 110 - 10000100 Rj Ri

174CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.78 STH (Store Half-word Data in Register to Memory)Stores the half-word data in "Ri" to memor

Strany 111 - Example: AND R2, @R3

175CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.79 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

Strany 113 - Example: ANDH R2, @R3

xvi 185"7.88 CALL (Call Subroutine)" is changed.( "extension for use as the branch destination address" → "extension"

Strany 114 - 10000110 Rj Ri

176CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.80 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

Strany 115 - Example: ANDB R2, @R3

177CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.81 STB (Store Byte Data in Register to Memory)Stores the byte data in "Ri" to memory address

Strany 116

178CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.82 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in "Rj"

Strany 117 - 10010100 Rj Ri

179CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.83 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in dedicated regi

Strany 118 - Example: OR R2, @R3

180CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.84 MOV (Move Word Data in Program Status Register to Destination Register)Moves the word data in the pr

Strany 119 - 10010101 Rj Ri

181CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.85 MOV (Move Word Data in Source Register to Destination Register)Moves the word data in general-purpos

Strany 120 - Example: ORH R2, @R3

182CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.86 MOV (Move Word Data in Source Register to Program Status Register)Moves the word data in general-pur

Strany 121 - 10010110 Rj Ri

183CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: MOV R3, PSR3R3FFF3 F8D5 FFF3 F8D5FFF3 F8D5PS PSxxxx xxxxBefore execution After executionInstruct

Strany 122 - Example: ORB R2, @R3

184CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.87 JMP (Jump)This is a branching instruction with no delay slot.Branches to the address indicated by &q

Strany 123

185CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.88 CALL (Call Subroutine)This is a branching instruction with no delay slot.After storing the address o

Strany 124 - 10011100 Rj Ri

xvii198"7.96 CALL:D (Call Subroutine)" is changed.( "CALL : D 120H LDI : 8 #0, R2 ; Instruction placed in delay slot" → &quo

Strany 125 - Example: EOR R2, @R3

186CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.89 CALL (Call Subroutine)This is a branching instruction with no delay slot.After storing the address o

Strany 126 - Data in Memory)

187CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.90 RET (Return from Subroutine)This is a branching instruction with no delay slot.Branches to the addre

Strany 127 - Example: EORH R2, @R3

188CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.91 INT (Software Interrupt)Stores the values of the program counter (PC) and program status (PS) to the

Strany 128 - 10011110 Rj Ri

189CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: INT #20H6809 6800 6809 68008088 8088FFFF F8F0R15 000FFF7Cxxxx xxxx 7FFFFFF87FFFFFFC80000000

Strany 129 - Example: EORB R2, @R3

190CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.92 INTE (Software Interrupt for Emulator)This software interrupt instruction is used for debugging. It

Strany 130

191CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: INTE6809 6800 6809 68008088 8088FFFF F8F0R15 000FFFD8xxxx xxxx 7FFFFFF87FFFFFFC80000000000F

Strany 131 - Example: BANDL #0, @R3

192CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.93 RETI (Return from Interrupt)Loads data from the stack indicated by "R15" to the program co

Strany 132

193CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: RETI8088 8088FFF3 F8F18088 8088FFF3 F8F1R15 xxxx xxxx7FFFFFF87FFFFFFC800000007FFFFFF87FFFFFFC8

Strany 133 - Example: BANDH #0, @R3

194CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.94 Bcc (Branch Relative if Condition Satisfied)This branching instruction has no delay slot.If the cond

Strany 134

195CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExecution cycles: Branch: 2 cyclesNot branch: 1 cycleInstruction format: Example: BHI label...label

Strany 135 - Example: BORL #1, @R3

xviii 238"7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed.( "Instruction bit pattern : 1000 0011 1111 1110&q

Strany 136

196CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.95 JMP:D (Jump)This branching instruction has a delay slot.Branches to the address indicated by "R

Strany 137 - Example: BORH #1, @R3

197CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.96 CALL:D (Call Subroutine)This is a branching instruction with a delay slot.After saving the address o

Strany 138

198CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: CALL:D labelLDI : 8 #0, R2 ; Instruction placed in delay slot...label: ; CALL: D instructio

Strany 139 - Example: BEORL #1, @R3

199CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.97 CALL:D (Call Subroutine)This is a branching instruction with a delay slot.After saving the address o

Strany 140

200CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: CALL : D @R1LDI : 8 #1, R1 ; Instruction placed in delay slotThe instruction placed in the de

Strany 141 - Example: BEORH #1, @R3

201CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.98 RET:D (Return from Subroutine)This is a branching instruction with a delay slot.Branches to the addr

Strany 142 - 10001000 u4 Ri

202CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: RET : D MOV R0, R1 ; Instruction placed in delay slotThe instruction placed in the delay slot

Strany 143 - 10001001 u4 Ri

203CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.99 Bcc:D (Branch Relative if Condition Satisfied)This is a branching instruction with a delay slot.If t

Strany 144 - 7.34 MUL (Multiply Word Data)

204CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExecution cycles: 1 cycleInstruction format: Example: BHI:D labelLDI :8 #255, R1 ; Instruction plac

Strany 145 - Example: MUL R2, R3

205CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.100 DMOV (Move Word Data from Direct Address to Register)Transfers, to "R13", the word data a

Strany 146 - 10101011 Rj Ri

xix263"A.1 Symbols Used in Instruction Lists" is chenged.● Symbols in Mnemonic and Operation Columns is changed.i8 ...( "128

Strany 147 - Example: MULU R2, R3

206CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.101 DMOV (Move Word Data from Register to Direct Address)Transfers the word data in "R13" to

Strany 148 - 10111111 Rj Ri

207CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)Transfers the

Strany 149 - Example: MULH R2, R3

208CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @88H, @R13+1414 2135 1414 21351414 2135R13 Memory00000088 FFFF1248FFFF124CFFFF1248FFF

Strany 150 - 10111011 Rj Ri

209CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)Transfers the

Strany 151 - Example: MULUH R2, R3

210CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @R13+, @54H8947 91AF8947 91AF8947 91AFR13 00000054 FFFF1248FFFF124CFFFF1248FFFF124C000

Strany 152 - 100101110100 Ri

211CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address)Decrements the

Strany 153

212CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @2CH, @ – R1582A2 82A9 82A2 82A982A2 82A9R15 Memory0000002C 7FFFFF847FFFFF880000002C7F

Strany 154 - 100101110101 Ri

213CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)Transfers the

Strany 155

214CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOV @R15+, @38H8343 834A8343 834A8343 834AR15 Memory00000038 7FFEEE807FFEEE84000000387FFE E

Strany 156 - DIV0U and DIV1 x 32

215CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.106 DMOVH (Move Half-word Data from Direct Address to Register)Transfers the half-word data at the dire

Strany 157 - Example: DIV1 R2

xx 267"Table A.2-6 Shift Instructions (9 Instructions)" is changed.( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} →

Strany 158 - 100101110111 Ri

216CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.107 DMOVH (Move Half-word Data from Register to Direct Address)Transfers the half-word data from "

Strany 159 - Example: DIV2 R2

217CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)Transfer

Strany 160 - 1001111101100000

218CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVH @88H, @R13+ 1374R13 00000088 FF000052FF000054FF00 0052R13FF00 0054Instruction bit patt

Strany 161 - 1001111101110000

219CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)Transfer

Strany 162 - 10110110 Rj Ri

220CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVH @R13+, @52H 8933R13 00000052 FF801220FF801222FF801220FF801222FF80 1220R13FF80 1222Inst

Strany 163 - 10110100 u4 Ri

221CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.110 DMOVB (Move Byte Data from Direct Address to Register)Transfers the byte data at the address indica

Strany 164 - "Ri"

222CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.111 DMOVB (Move Byte Data from Register to Direct Address)Transfers the byte data from "R13"

Strany 165 - 10110010 Rj Ri

223CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)Moves the byt

Strany 166 - 10110000 u4 Ri

224CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVB @71H, @R13+ 99R13 Memory00000071xxxx xx 88001234880012358800 1234R138800 1235Instructio

Strany 167 - 10110001 u4 Ri

225CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)Transfers the

Strany 168 - 10111010 Rj Ri

1CHAPTER 1FR FAMILY OVERVIEWThis chapter describes the features of the FR FAMILY CPU core, and provides sample configurations.1.1 Features of the FR

Strany 169

226CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: DMOVB @R13+, @57H 55 5555R13 Memory00000057xxxx xx FF801220FF801221FF80 1220R13FF80 1221Instr

Strany 170 - 10111001 u4 Ri

227CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.114 LDRES (Load Word Data in Memory to Resource)Transfers the word data at the address indicated by &qu

Strany 171 - 8765 43210000 0000

228CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.115 STRES (Store Word Data in Resource to Memory)Transfers the word data at the resource on channel &qu

Strany 172 - 0005 43210000 0000

229CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.116 COPOP (Coprocessor Operation)Transfers the 16-bit data consisting of parameters "CC", &qu

Strany 173 - 0000 00210000 0000

230CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPOP #15, #1, CR3, CR416-bit data is transferred through the bus to the coprocessor indicated b

Strany 174 - 00000100 Rj Ri

231CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)Transfers the 16-bit data consisting

Strany 175 - 00000000 Rj Ri

232CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPLD #15, #4, R8, CR116-bit data is transferred through the bus to the coprocessor indicated by

Strany 176 - 0010 Rio8

233CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)Transfers the 16-bit data consisting

Strany 177 - 00000011 u4 Ri

234CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPST #15, #4, CR2, R416-bit data is transferred through the bus to the coprocessor indicated by

Strany 178 - 000001110000 Ri

235CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)Transfers the 16-bit data consisting

Strany 179 - 000001111000 Rs

2CHAPTER 1 FR FAMILY OVERVIEW1.1 Features of the FR Family CPU CoreThe FR family CPU core features proprietary Fujitsu architecture and is designed f

Strany 180 - Example: LD @ R15 +, MDH

236CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: COPSV #15, #4, CR2, R416-bit data is transferred through the bus to the coprocessor indicated by

Strany 181 - 0000011110010000

237CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.120 NOP (No Operation)This instruction performs no operation. NOP (No Operation)Assembler format: NOPO

Strany 182 - Example: LD @ R15 +, PS

238CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.121 ANDCCR (And Condition Code Register and Immediate Data)Takes the logical AND of the byte data in th

Strany 183 - 00000101 Rj Ri

239CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.122 ORCCR (Or Condition Code Register and Immediate Data)Takes the logical OR of the byte data in the c

Strany 184 - 00000001 Rj Ri

240CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)Transfers the immediate data to the inte

Strany 185 - 0100 Rio8

241CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.124 ADDSP (Add Stack Pointer and Immediate Data)Adds 4 times the immediate data as a signed extended va

Strany 186 - 00000110 Rj Ri

242CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.125 EXTSB (Sign Extend from Byte Data to Word Data)Extends the byte data indicated by "Ri" to

Strany 187 - 00000010 Rj Ri

243CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.126 EXTUB (Unsign Extend from Byte Data to Word Data)Extends the byte data indicated by "Ri"

Strany 188 - 0110 Rio8

244CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.127 EXTSH (Sign Extend from Byte Data to Word Data)Extends the half-word data indicated by "Ri&quo

Strany 189 - 00010100 Rj Ri

245CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)Extends the half-word data indicated by "Ri

Strany 190 - 00010000 Rj Ri

3CHAPTER 1 FR FAMILY OVERVIEW1.2 Sample Configuration of an FR Family DeviceFR family devices have block configuration with bus connections between i

Strany 191 - 0011 Rio8

246CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.129 LDM0 (Load Multiple Registers)The "LDM0" instruction accepts registers in the range R0 to

Strany 192 - 00010011 u4 Ri

247CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LDM0 (R3, R4) 90BC93638343 834A xxxx xxxx7FFFFFC07FFFFFC47FFFFFC8R157FFF FFC0R4R3Instruction

Strany 193 - 000101110000 Ri

248CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.130 LDM1 (Load Multiple Registers)The LDM1 instruction accepts registers in the range R8 to R15 as memb

Strany 194 - 000101111000 Rs

249CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LDM1 (R10, R11, R12) Table 7.130-1 Bit Values and Register Numbers for "reglist" (LD

Strany 195 - 0001011110010000

250CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.131 STM0 (Store Multiple Registers)The "STM0" instruction accepts registers in the range R0 t

Strany 196 - 00010101 Rj Ri

251CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: STM0 (R2, R3) 90BC93638343 834A xxxx xxxx7FFFFFC07FFFFFC47FFFFFC8R157FFF FFC8R3R2Instruction b

Strany 197 - 00010001 Rj Ri

252CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.132 STM1 (Store Multiple Registers)The "STM1" instruction accepts registers in the range R8 t

Strany 198 - 0101 Rio8

253CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: STM1 (R10, R11, R12) 90BC93638DF7 88E4 xxxx xxxx7FFFFFC47FFFFFC87FFFFFCCR157FFF FFCCR12R10Inst

Strany 199 - 00010110 Rj Ri

254CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.133 ENTER (Enter Function)This instruction is used for stack frame generation processing for high level

Strany 200 - 00010010 Rj Ri

255CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: ENTER #0CH 7FFF FFF8 7FFFFFF87FFFFFFC80000000R14Instruction bit pattern : 0000 1111 0000 0011

Strany 201 - 0111 Rio8

4CHAPTER 1 FR FAMILY OVERVIEW1.3 Sample Configuration of the FR Family CPUThe FR family CPU core features a block configuration organized around gene

Strany 202

256CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.134 LEAVE (Leave Function)This instruction is used for stack frame release processing for high level la

Strany 203

257CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: LEAVE7FFF FFEC 7FFFFFF87FFFFFFC80000000R14 7FFF FFF47FFFFFF47FFFFFF07FFFFFEC8000 00008000 00

Strany 204

258CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.135 XCHB (Exchange Byte Data)Exchanges the contents of the byte address indicated by "Rj" and

Strany 205 - 8765 4321

259CHAPTER 7 DETAILED EXECUTION INSTRUCTIONSExample: XCHB @R1, R0R1 800000018000000280000003800000018000000280000003xxxxxxxxFDR1 788000 00028000

Strany 206 - Status Register)

260CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS

Strany 207 - FFF3 F8D5

261APPENDIXThe appendix section includes lists of CPU instructions used in the FR family, as well as instruction map diagrams.APPENDIX A Instruction

Strany 208 - 7.87 JMP (Jump)

262APPENDIX A Instruction ListsAPPENDIX A Instruction ListsAppendix A includes a description of symbols used in instruction lists, plus the instructi

Strany 209 - FF80 0004

263APPENDIX A Instruction ListsA.1 Symbols Used in Instruction ListsThis section describes symbols used in the FR family instruction lists. Symbols

Strany 210 - 7.89 CALL (Call Subroutine)

264APPENDIX A Instruction Lists● Format ColumnA to F ... format TYPE-A through F as described in Section "6.1 Instruction Formats"

Strany 211 - 1001011100100000

265APPENDIX A Instruction ListsA.2 Instruction ListsThe full instruction set of the FR family CPU is 165 instructions, consisting of the following s

Strany 212 - 7.91 INT (Software Interrupt)

5CHAPTER 2MEMORY ARCHITECTUREThis chapter describes memory space in the FR family CPU.Memory architecture includes the allocation of memory space as w

Strany 213 - Example: INT #20H

266APPENDIX A Instruction ListsTable A.2-2 Compare Instructions (3 Instructions) Mnemonic Format OP CYCFLAGNZVCOperation RemarksCMP Rj, RiCMP

Strany 214 - 1001111100110000

267APPENDIX A Instruction ListsTable A.2-5 Multiply/Divide Instructions (10 Instructions) Mnemonic Format OP CYCFLAGNZVCOperation RemarksMUL R

Strany 215 - Example: INTE

268APPENDIX A Instruction ListsNote:The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have

Strany 216 - 1001011100110000

269APPENDIX A Instruction ListsNote:The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have

Strany 217 - Example: RETI

270APPENDIX A Instruction ListsNotes:• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F form

Strany 218

271APPENDIX A Instruction ListsNotes:• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F form

Strany 219 - 1110 cc rel8

272APPENDIX A Instruction ListsNote:The field "dir" in the TYPE-D instruction format has the following relation to the values "dir8&qu

Strany 220 - 7.95 JMP:D (Jump)

273APPENDIX A Instruction ListsNotes:• In the "ADD SP" instruction, the field "s8" in the TYPE-D instruction format has the follo

Strany 221 - 7.96 CALL:D (Call Subroutine)

274APPENDIX B Instruction MapsAPPENDIX B Instruction MapsThis appendix presents FR family instruction map and "E" format.B.1 Instruction M

Strany 222

275APPENDIX B Instruction MapsB.1 Instruction MapThis section shows instruction maps for FR family CPU. Instruction MapTable B.1-1 Instruction MapH

Strany 223 - 7.97 CALL:D (Call Subroutine)

FUJITSU LIMITEDFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUAL

Strany 224

6CHAPTER 2 MEMORY ARCHITECTURE2.1 FR Family Memory SpaceThe FR family controls memory space in byte units, and provides linear designation of 32-bit

Strany 225 - 1001111100100000

276APPENDIX B Instruction MapsB.2 "E" FormatThis section shows "E" format for FR family CPU. "E" Format-: UndefinedTab

Strany 226

277INDEXINDEXThe index follows on the next page.This is listed in alphabetical order.

Strany 227

278INDEXIndexAADDADD (Add 4-bit Immediate Data to Destination Register)...73ADD (Add Word Data of Source R

Strany 228 - 1111 cc rel8

279INDEXBit PatternsRelation between Bit Patterns "Ri" and "Rj" and Register Values... 64BORHBOR

Strany 229 - 00001000

280INDEXExamples of Programing Delayed Branching Instructions...62Overview of Branching with Delayed Branching

Strany 230 - 00011000

281INDEXDMOVB (Move Byte Data from Register to Direct Address)... 222DMOVHDMOVH (Move Half-word Data from Di

Strany 231 - Address)

282INDEXInterlocking Produced by Reference to "R15" and General-purpose Registers after Changing the "S" Flag ...

Strany 232 - Example: DMOV @88H, @R13+

283INDEXPrecautionary Information for Use of "INT" Instructions... 45Time to Start of Trap Processin

Strany 233

284INDEXLDI:8 (Load Immediate 8-bit Data to Destination Register)...149Load Multiple RegistersLDM0 (Load Mul

Strany 234 - Example: DMOV @R13+, @54H

285INDEXNNMIRelation of Step Trace Traps to "NMI" and External Interrupts... 47No OperationNOP (N

Strany 235

7CHAPTER 2 MEMORY ARCHITECTURE2.1.1 Direct Address AreaThe lower portion of the address space is used for the direct address area. Instructions that

Strany 236 - Instruction bit pattern :

286INDEXInterrupt Level Mask Register (ILM: Bit 20 to bit 16)...19LD (Load Word Data in Memor

Strany 237

287INDEXEORB (Exclusive Or Byte Data of Source Register to Data in Memory)... 104EORH (Exclusive Or Half-word Data of So

Strany 238 - Example: DMOV @R15+, @38H

288INDEXSystem Stack PointerFunctions of the System Stack Pointer and User Stack Pointer ...28System Sta

Strany 239

CM71-00101-5EFUJITSU SEMICONDUCTOR • CONTROLLER MANUALFR Family32-BIT MICROCONTROLLERINSTRUCTION MANUALDecember 2007 the fifth editionPublished FUJITS

Strany 241

8CHAPTER 2 MEMORY ARCHITECTURE2.1.2 Vector Table AreaAn area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to

Strany 242 - Example: DMOVH @88H, @R13+

9CHAPTER 2 MEMORY ARCHITECTURE Contents of Vector Table AreasA vector table is composed of entry addresses for each of the "EIT" processin

Strany 243

10CHAPTER 2 MEMORY ARCHITECTURE2.2 Bit Order and Byte OrderThis section describes the order in which three types of data, 8, 16, and 32 bits, are pla

Strany 244 - Example: DMOVH @R13+, @52H

11CHAPTER 2 MEMORY ARCHITECTURE2.3 Word AlignmentIn the FR family, the type of data length used determines restrictions on thedesignation of memory a

Strany 245 - 00001010

12CHAPTER 2 MEMORY ARCHITECTURE

Strany 246 - 00011010

13CHAPTER 3REGISTER DESCRIPTIONSThis chapter describes the registers used in the FR family CPU.3.1 FR Family Register Configuration3.2 General-purpo

Strany 247

14CHAPTER 3 REGISTER DESCRIPTIONS3.1 FR Family Register ConfigurationFR family devices use two types of registers, general-purpose registers and dedi

Strany 248 - Example: DMOVB @71H, @R13+

15CHAPTER 3 REGISTER DESCRIPTIONS3.2 General-purpose RegistersThe FR family CPU uses general-purpose registers to hold the results of various calcula

Strany 250 - Example: DMOVB @R13+, @57H

16CHAPTER 3 REGISTER DESCRIPTIONS● R14 (Frame Pointer: FP)• Index register for load/store to memory instructions[Example: LD @(R14, disp10), Ri]• Fra

Strany 251 - 10111100 u4 Ri

17CHAPTER 3 REGISTER DESCRIPTIONS3.3 Dedicated RegistersThe FR family has six 32-bit registers reserved for various special purposes, plus one 64-bit

Strany 252 - 10111101 u4 Ri

18CHAPTER 3 REGISTER DESCRIPTIONS3.3.1 Program Counter (PC)This register indicates the address containing the instruction that is currently executing

Strany 253 - CRiCRjCC(n+2)

19CHAPTER 3 REGISTER DESCRIPTIONS3.3.2 Program Status (PS) The program status (PS) indicates the status of program execution, and consists of the fol

Strany 254 - 0000000100110100

20CHAPTER 3 REGISTER DESCRIPTIONSFigure 3.3-4 "ILM" Register Functions● Range of ILM Program Setting ValuesIf the original value of the re

Strany 255

21CHAPTER 3 REGISTER DESCRIPTIONS Condition Code Register (CCR: Bit 07 to bit 00)● Bit Configuration of the "CCR" Figure 3.3-6 Bit Config

Strany 256 - (Coprocessor register)

22CHAPTER 3 REGISTER DESCRIPTIONS Note on PS RegisterBecause of prior processing of the PS register by some commands, a break may be brought in an i

Strany 257

23CHAPTER 3 REGISTER DESCRIPTIONS3.3.3 Table Base Register (TBR)The Table Base Register (TBR) designates the table containing the entry address for &

Strany 258

24CHAPTER 3 REGISTER DESCRIPTIONS Table Base Register ConfigurationFigure 3.3-8 shows the bit configuration of the table base register. Figure 3.3-

Strany 259

25CHAPTER 3 REGISTER DESCRIPTIONS3.3.4 Return Pointer (RP)The return pointer (RP) is a register used to contain the program counter (PC) value during

Strany 260

iPREFACE Objectives and intended readerThe FR* family CPU core features proprietary Fujitsu architecture and is designed for controllerapplications u

Strany 261 - 8343 834C8343 834A

26CHAPTER 3 REGISTER DESCRIPTIONS Return Pointer ConfigurationFigure 3.3-11 shows the bit configuration of the return pointer. Figure 3.3-11 Retur

Strany 262 - 10000011

27CHAPTER 3 REGISTER DESCRIPTIONS3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP)The system stack pointer (SSP) and user stack pointer (USP

Strany 263 - 10010011

28CHAPTER 3 REGISTER DESCRIPTIONSFigure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15" when "S

Strany 264 - 11111 10100

29CHAPTER 3 REGISTER DESCRIPTIONS3.3.6 Multiplication/Division Register (MD)The multiplication/division register (MD) is a 64-bit register used to co

Strany 265 - 10100011

30CHAPTER 3 REGISTER DESCRIPTIONS Configuration of the "MD" RegisterFigure 3.3-17 shows the bit configuration of the "MD". Figu

Strany 266 - 100101111000 Ri

31CHAPTER 4RESET AND "EIT"PROCESSINGThis chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of

Strany 267 - 100101111001 Ri

32CHAPTER 4 RESET AND "EIT" PROCESSING4.1 Reset Processing4.2 Basic Operations in "EIT" Processing4.3 Interrupts4.4 Exception

Strany 268 - 100101111010 Ri

33CHAPTER 4 RESET AND "EIT" PROCESSING4.1 Reset ProcessingA reset is a means of forcibly terminating the currently executing process, initi

Strany 269 - 100101111011 Ri

34CHAPTER 4 RESET AND "EIT" PROCESSING4.2 Basic Operations in "EIT" ProcessingInterrupts, exceptions and traps are similar operat

Strany 270 - 10001100

35CHAPTER 4 RESET AND "EIT" PROCESSING Vector Table ConfigurationVector tables are located in the main memory, occupying an area of 1 Kbyt

Strany 271 - Example: LDM0 (R3, R4)

ii Organization of this manualThis manual consists of the following 7 chapters and 1 appendix:CHAPTER 1 FR FAMILY OVERVIEWThis chapter describes t

Strany 272 - 10001101

36CHAPTER 4 RESET AND "EIT" PROCESSING Saved RegistersExcept in the case of reset processing, the values of the "PS" and "P

Strany 273

37CHAPTER 4 RESET AND "EIT" PROCESSING4.3 InterruptsInterrupts originate independently of the instruction sequence. They are processed by s

Strany 274 - 10001110

38CHAPTER 4 RESET AND "EIT" PROCESSING4.3.1 User InterruptsUser interrupts originate as requests from peripheral circuits. Each interrupt r

Strany 275 - Example: STM0 (R2, R3)

39CHAPTER 4 RESET AND "EIT" PROCESSING Time to Start of Interrupt ProcessingThe time required to start interrupt processing can be express

Strany 276 - 10001111

40CHAPTER 4 RESET AND "EIT" PROCESSING4.3.2 Non-maskable Interrupts (NMI)Non-maskable interrupts (NMI) are interrupts that cannot be masked

Strany 277

41CHAPTER 4 RESET AND "EIT" PROCESSING "PC" Values Saved for Non-maskable InterruptsWhen an "NMI" is accepted by the p

Strany 278 - 7.133 ENTER (Enter Function)

42CHAPTER 4 RESET AND "EIT" PROCESSING4.4 Exception ProcessingExceptions originate from within the instruction sequence. Exceptions are pro

Strany 279

43CHAPTER 4 RESET AND "EIT" PROCESSING4.4.1 Undefined Instruction ExceptionsUndefined instruction exceptions are caused by attempts to exec

Strany 280 - 7.134 LEAVE (Leave Function)

44CHAPTER 4 RESET AND "EIT" PROCESSING4.5 TrapsTraps originate from within the instruction sequence. Traps are processed by first saving th

Strany 281 - Example: LEAVE

45CHAPTER 4 RESET AND "EIT" PROCESSING4.5.1 "INT" InstructionsThe "INT" instruction is used to create a software trap.T

Strany 282 - 10001010 Rj Ri

iiiCopyright ©1997-2007 FUJITSU LIMITED All rights reserved.• The contents of this document are subject to change without notice. Customers are advise

Strany 283

46CHAPTER 4 RESET AND "EIT" PROCESSING4.5.2 "INTE" InstructionThe "INTE" instruction is used to create a software trap

Strany 284

47CHAPTER 4 RESET AND "EIT" PROCESSING4.5.3 Step Trace TrapsStep trace traps are traps used by debuggers. This type of trap can be created

Strany 285 - APPENDIX

48CHAPTER 4 RESET AND "EIT" PROCESSING4.5.4 Coprocessor Not Found TrapsCoprocessor not found traps are generated by executing coprocessor i

Strany 286 - APPENDIX A Instruction Lists

49CHAPTER 4 RESET AND "EIT" PROCESSING4.5.5 Coprocessor Error TrapA coprocessor error trap is generated when an error has occurred in a cop

Strany 287 - ● Symbols in Operation Column

50CHAPTER 4 RESET AND "EIT" PROCESSING Saving and Restoring Coprocessor Error InformationWhen a coprocessor is used in a multi-tasking env

Strany 288 - ● FLAG Column

51CHAPTER 4 RESET AND "EIT" PROCESSING4.6 Priority LevelsWhen multiple "EIT" requests occur at the same time, priority levels are

Strany 289 - A.2 Instruction Lists

52CHAPTER 4 RESET AND "EIT" PROCESSING Priority of Multiple ProcessesWhen the acceptance of an "EIT" source results in the maski

Strany 290

53CHAPTER 5PRECAUTIONARYINFORMATION FOR THE FRFAMILY CPUThis chapter presents precautionary information related to the use of the FR family CPU.5.1 P

Strany 291

54CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.1 Pipeline OperationThe FR family CPU processes all instructions using a 5-stage pipelin

Strany 292 - → u4=udisp6 >> 2

55CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.2 Pipeline Operation and Interrupt ProcessingThe FR family CPU processes all instruction

Strany 294 - → rel11=(label12 – PC – 2)/2

56CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.3 Register HazardsThe FR family CPU executes program steps in the order in which they ar

Strany 295

57CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU InterlockingInstructions which are relatively slow in loading data to the CPU may cause

Strany 296 - → dir=dir10 >> 2

58CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4 Delayed Branching ProcessingBecause the FR family CPU features pipeline operation, bra

Strany 297 - → u8=u10 >> 2

59CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU•AND Rj, @Ri ANDH Rj, @RiANDB Rj, @RiOR Rj, @RiORH Rj, @RiORB Rj, @RiEOR Rj, @RiEORH Rj, @

Strany 298 - APPENDIX B Instruction Maps

60CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4.1 Processing Non-delayed Branching InstructionsThe FR family CPU processes non-delayed

Strany 299 - B.1 Instruction Map

61CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU5.4.2 Processing Delayed Branching InstructionsThe FR family CPU processes delayed branchi

Strany 300 - B.2 "E" Format

62CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Examples of Programing Delayed Branching InstructionsAn example of programing a delayed

Strany 301

63CHAPTER 6INSTRUCTION OVERVIEWThis chapter presents an overview of the instructions used with the FR family CPU.All FR family CPU instructions are in

Strany 302

64CHAPTER 6 INSTRUCTION OVERVIEW6.1 Instruction FormatsThe FR family CPU uses six types of instruction format, TYPE-A through TYPE-F. Instruction Fo

Strany 303

65CHAPTER 6 INSTRUCTION OVERVIEW Relation between Bit Pattern "Rs" and Register ValuesTable 6.1-2 shows the relation between dedicated reg

Strany 304

vCONTENTSCHAPTER 1 FR FAMILY OVERVIEW ... 11.1 Features of the FR Family C

Strany 305

66CHAPTER 6 INSTRUCTION OVERVIEW6.2 Instruction Notation FormatsFR family CPU instructions are written in the following three notation formats.• Calc

Strany 306

67CHAPTER 7DETAILED EXECUTIONINSTRUCTIONSThis chapter presents each of the execution instructions used by the FR family assembler, in reference format

Strany 307

68CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)7.5 ADDN (Add Word Data o

Strany 308

69CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.40 DIV1 (Main Process of Division)7.41 DIV2 (Correction when Remainder is 0)7.42 DIV3 (Correction when R

Strany 309

70CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.77 STH (Store Half-word Data in Register to Memory)7.78 STH (Store Half-word Data in Register to Memory)

Strany 310

71CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.110 DMOVB (Move Byte Data from Direct Address to Register)7.111 DMOVB (Move Byte Data from Register to D

Strany 311

72CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.1 ADD (Add Word Data of Source Register to Destination Register)Adds word data in "Rj" to word

Strany 312

73CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.2 ADD (Add 4-bit Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit i

Strany 313 - 32-BIT MICROCONTROLLER

74CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.3 ADD2 (Add 4-bit Immediate Data to Destination Register)Adds the result of the higher 28 bits of 4-bit

Strany 314

75CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)Adds the word data in &qu

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