Fujitsu CM8063501293407 manuály

Fujitsu CM8063501293407 Datový list (236 strany)

Značka: Fujitsu | Kategorie: Procesory | Velikost: 4.59 MB |

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Processor E5-1600/E5

1

Table of Contents

3

Datasheet Volume One of Two

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Revision History

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1 Overview

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Processor

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1.1.2 Supported Technologies

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1.2 Interfaces

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1.2.2 PCI Express*

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Transaction

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1.2.4 Intel

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1.3 Power Management Support

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1.5 Package Summary

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1.6 Terminology

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1.7 Related Documents

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1.9 State of Data

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2 Interfaces

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2.2 PCI Express* Interface

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2.2.1.1 Transaction Layer

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2.2.1.2 Data Link Layer

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2.2.1.3 Physical Layer

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2.4 Intel

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2.5.1.1 Thermal Management

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2.5.2 Client Command Suite

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Reserved

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# of Domains

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Byte# 5

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2.5.2.3 GetTemp()

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2.5.2.4 RdPkgConfig()

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2.5.2.5 WrPkgConfig()

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Channel Temperature Data

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816232431

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DRAM Power Limit Performance

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CPU ID Data

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CPU code patch revision

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Current Config Limit Data

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RESERVED

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Accumulated Energy Status

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Accumulated CPU Energy

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Accumulated CPU Throttle Time

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2.5.2.7 RdIAMSR()

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Cores 0,1,2...12

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Thread (0,1) Mask for Core10

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2.5.2.8 RdPCIConfig()

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2.5.2.9 RdPCIConfigLocal()

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DeviceBus Function Register

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2.5.2.10 WrPCIConfigLocal()

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2.5.3.1 Power-up Sequencing

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2.5.3.2 Device Discovery

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2.5.3.3 Client Addressing

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2.5.3.4 C-states

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2.5.3.5 S-states

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2.5.3.6 Processor Reset

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2.5.4 Multi-Domain Commands

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2.5.5.1 Abort FCS

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2.5.5.2 Completion Codes

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2.5.7.1 Format

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2.5.7.2 Interpretation

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3 Technologies

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3.1.2 Intel

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VT-x Features

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3.1.3 Intel® VT-d Objectives

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3.2 Security Technologies

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3.2.3 AES Instructions

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3.3 Intel

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Secure Key

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3.4 Intel

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OS Guard

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3.6 Intel

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Turbo Boost Technology

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3.10 Intel

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Dynamic Power Technology

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4 Power Management

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Table 4-6. Intel® QPI States

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4.2.2 Low-Power Idle States

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C1 C1E C6C3

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4.2.4.1 Core C0 State

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4.2.4.2 Core C1/C1E State

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4.2.4.3 Core C3 State

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4.2.4.4 Core C6 State

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4.2.4.5 Delayed Deep C-States

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4.2.5.1 Package C0

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4.2.5.2 Package C1/C1E

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4.2.5.3 Package C2 State

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4.2.5.4 Package C3 State

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4.2.5.5 Package C6 State

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4.3.1 CKE Power-Down

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4.3.2.1 Self Refresh Entry

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4.3.2.2 Self Refresh Exit

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4.3.2.3 DLL and PLL Shutdown

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5 Thermal Management

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CASE_MAX_B

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CC activation

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Table 5-1. T

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5.1.5 Thermal Metrology

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5.2.1 Processor Temperature

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Intel® Xeon® Processor E5

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Design Guide

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5.2.2.2 Clock Modulation

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5.2.4 PROCHOT_N Signal

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5.2.5 THERMTRIP_N Signal

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Interface

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6 Signal Descriptions

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6.5 PECI Signal

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6.7 JTAG and TAP Signals

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Miscellaneous Signals

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7 Electrical Specifications

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BCLK{0/1}_DN)

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7.1.6.1 PLL Power Supply

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7.1.9.2 Decoupling Guidelines

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contains further

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Table 7-2. SVID Address Usage

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7.2 Signal Group Summary

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7.5 Mixing Processors

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7.8 DC Specifications

145

Table 7-13. Processor V

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Figure 7-3. Processor V

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7.8.2.1 V

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Overshoot Specifications

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Time [us]

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Unit Figure Notes

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VHavg (mV)

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250 + 0.5 (VHavg - 700)

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550 + 0.5 (VHavg - 700)

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7.9 Signal Quality

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7.9.3 Intel

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Specifications

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7.9.5.3 Activity Factor

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1.3335 V 0.2835 V 3 ns 5 ns

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1.2600 V 0.210 V 5 ns 5 ns

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8 Processor Land Listing

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8.2 Listing by Land Number

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9 Package Mechanical

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Intel® Xeon®

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9.8 Processor Materials

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9.9 Processor Markings

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10.1 Introduction

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(Boxed 25.5 mm Tall Passive H

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Keepout Zones

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LEGEND, SHEETS 1 & 2 ONLY

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2200 MISSION COLLEGE BLVD

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P.O. BOX 58119

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SANTA CLARA, CA 95052-8119

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Bases Only

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Support (ILM-RS)

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°C. Meeting the

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(Blade + 1U + 2U Rack)

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10.4 Boxed Processor Contents

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